Resonant tunneling diodes (RTDs) have the potential for use as compact and coherent terahertz (THz) sources operating at room temperature. In this paper, sub-THz and THz oscillators with RTDs integrated on planar circuits are described. Fundamental oscillation up to 0.65 THz and harmonic oscillation up to 1.02 THz were obtained at room temperature in our recent study. Limiting factors for oscillation frequency and output power are theoretically analyzed including tunneling and transit-time effects and parasitic elements. Oscillation frequency and its dependence on RTD size are in good agreement with the measured results. Based on this result, it is shown that fundamental oscillation up to 2.3 THz and an output power of 60 µW at 1 THz are theoretically expected by improving the structures of the RTD and the antenna. Voltage-controlled oscillation, which is useful for the precise control of frequency, is observed in the RTD oscillators. Coherent power combining in an array configuration to achieve high output power as well as mutual injection locking between the array elements are also described.

The pulsed method for selecting tunnel diodes is suitable for their simultaneous rapid sorting in small batches (up to 5–8 specimens); it serves to evaluate the amplitude and speed characteristics of any diode of a batch and it contributes only a small error (for a 1-mm line thickness on the screen and an image height of 50–100 mm the error amounts to 1–2%). Translated from Izmeritel'naya Tekhnika, No. 3, pp. 37–38, March, 1967.

The basic principle of operation of each bit in a matrix of image detectors is described, together with the derivation of appropriate operating formulas. The necessary circuitry to make a functional two-dimensional array is also described, including the scanning circuitry integrally constructed with the photodetector matrix. The necessary design considerations for operation of the matrix are discussed in the context of the currently operating 10-by-10 array. Extension of the principles to larger arrays is outlined in the two modes of array scanning considered, with special reference to spatial noise problems. The paper concludes with reference to other applications of the basic principle, such as card reading.

This paper appears in: Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003. International Conference on Publication Date: 3-5 Sept. 2003 On page(s): 133- 136 ISSN: ISBN: 0-7803-7826-1 INSPEC Accession Number: 7845871 Posted online: 2003-09-29 16:22:19.0 Degraded junction leakage current in scaled MOSFETs due to enhanced band-to-band tunneling (i.e. local Zener effect) is characterized based on a modified band-to-band tunneling model. To suppress the severe drain leakage current in the presence of high-dose halo implants, the impact of implant conditions on drain leakage current is estimated based on implant induced damage (point defect) profiles.

The metal oxide semiconductor field effect transistor (MOSFET) is scaling to a “tunneling epoch”, in which multiple leakage current induced by different tunneling effects exist. The complementary Si-based tunneling transistors are presented in this paper. The working principle of this device is investigated in detail. It is found that the band-to-band tunneling current is be controlled by the gate-to-source voltage. Due to the reverse biased p-i-n diode structure, an ultra-low leakage current is achieved. The sub-threshold swing of TFET is not limited by kt/q, which is the physical limit of the MOSFET. Using the CMOS compatible processes, the complementary TFETs (CTFET) are fabricated on one wafer. From a circuit point of view, the compatibility between TFET and MOSFET enables the transfer of CMOS circuits to CTFET circuits.

A formula is derived, which shows that the subthreshold swing of field-effect interband tunnel transistors is not limited to 60 mV/dec as in the MOSFET. This formula is consistent with two recent reports of interband tunnel transistors, which show lower than 60-mV/dec subthreshold swings and provides two simple design principles for configuring these transistors. One of these principles suggests placing the gate adjacent to the tunnel junction. Modeling of this configuration verifies that sub-60-mV/dec swing is possible.

We have demonstrated a 70-nm n-channel tunneling field-effect transistor (TFET) which has a subthreshold swing (SS) of 52.8 mV/dec at room temperature. It is the first experimental result that shows a sub-60-mV/dec SS in the silicon-based TFETs. Based on simulation results, the gate oxide and silicon-on-insulator layer thicknesses were scaled down to 2 and 70 nm, respectively. However, the ON/ OFF current ratio of the TFET was still lower than that of the MOSFET. In order to increase the on current further, the following approaches can be considered: reduction of effective gate oxide thickness, increase in the steepness of the gradient of the source to channel doping profile, and utilization of a lower bandgap channel material

Tunneling currents in reverse-biased base-emitter junctions are investigated and analyzed. Guided by a simple analytic theory, shallow n+-p junctions are designed with a variety of different concentration profiles. Measurements of the dc electrical characteristics indicate a significant Zener tunneling component in the reverse diode current. The appearance of tunneling is ascertained by the temperature dependence, which also allows a clear distinction of other current mechanisms. The sensitivity of the current to the details of the doping profile is theoretically explained in terms of the maximum electric field in the junction and verified by SIMS andC-Vprofiling techniques. TheC-Vdata are analyzed in a novel way to obtain experimental data on the maximum electric field making the conclusions valid for any arbitrary junction. The implications of the presence of high electric fields in shallow junctions are discussed with respect to scaling bipolar transistors.

Implanted-diffused As layers in Si have been well-characterized and have been used in fabricating low-voltage n-p junctions. It is shown that these As layers form linearly graded junctions with a uniform B-doped background (ρ ≃ 0.006 Ω.cm). The grade constant of the As profile at the junction is known sufficiently well as a function of As dose, diffusion time, and temperature to allow quantitative use of existing tunneling and avalanche theories for the calculation of the reverse I-V curves. Following a verification of the calculated I-V curves and their temperature dependence as a function of grade constant, calculated curves are presented which correlate As implant dose and diffusion with junction breakdown voltage, breakdown impedance, and temperature coefficient of reverse voltage. The temperature coefficient is shown to change from negative to positive as the transition from tunneling to avalanche occurs. In addition, the relative importance of tunneling and multiplied-generation current as a function of current density is elucidated for any particular As layer grade constant.

This paper explores the limit of bulk (or partially-depleted SOI) CMOS scaling. A feasible design for 25 nm (channel length) CMOS, without continued scaling of oxide thickness and power supply voltage, is presented. A highly 2D nonuniform profile (super-halo) is shown to yield low off-currents while delivering a significant performance advantage for a 1.0 V power supply. Several key issues, including source-drain doping requirements, band-to-band tunneling, and poly depletion effects, are examined and quantified. It is projected, based on Monte-Carlo simulations, that the delay performance of 25 nm CMOS is 3× higher than 100 nm CMOS, and that the nFET fT exceeds 250 GHz