There are a lot of factors causing the monitor not ........

There are a lot of factors causing the monitor not to work well. Examination by the technician generally involves two steps: preliminary testing for facts finding and minor problems solving, and/or followed by further hardware-repairing. This paper describes the using of XS-Board and the Xilinx-FPGA within it to create preliminary testing tool for VGA troubleshooting. The goal of this research is to evaluate how effective the using of XS-Board with FPGA XC4005XL to implement a preliminary testing tool for VGA troubleshooting. The system will generate pictures in certain patterns and colors periodically to help technician in observing the monitor. The experiment shows that XS-Board with FPGA XC4005XL inside it is capable in handling the signaling for VGA monitor to display 64 colors almost fullscreen. With only consume 15% of logic cell resources; this system is efficient enough and ready to be improved further. One of its critical characteristics is that the internal clock generator of XC4005XL has 10% tolerant in frequency variation resulting in imperfect display of fullscreen mode. Abstract in Bahasa Indonesia : Ada banyak faktor penyebab kenapa monitor tidak berfungsi dengan baik. Pemeriksaan oleh tukang servis biasanya meliputi dua tahap: pemeriksaan pendahuluan untuk mencari fakta teknis dan menyelesaikan kerusakan kecil, dan/atau dilanjutkan dengan perbaikan perangkat keras lebih lanjut. Makalah ini menjelaskan penggunaan XS-Board yang dilengkapi dengan FPGA dari Xilinx untuk menciptakan perlengkapan pemeriksaan pendahuluan untuk perawatan VGA. Tujuan penelitian ini adalah untuk mengetahui seberapa efektif penggunaan XS-Board dengan FPGA XC4005 di dalamnya guna mengimplementasikan sebuah alat pemeriksa awal untuk perbaikan monitor VGA. Metode yang dilakukan adalah dengan membangkitkan gambar menggunakan pola-pola dan warna tertentu secara periodik untuk membantu tukang servis dalam pemeriksaan. Percobaan menunjukkan bahwa XS-Board dengan XC4005XL di dalamnya mampu menghasilkan sinyal-sinyal kontrol untuk VGA sehingga mampu menampilkan hingga 64 warna dengan tampilan layar hampir penuh (fullscreen). Dengan hanya menggunakan 15% dari sumberdaya FPGA yang tersedia, sistem ini dirasa cukup efisien dan bisa dikembangkan lagi lebih lanjut. Salah satu karakteristik penting dari sistem ini adalah pembangkit clock internal dari XC4005XL yang memiliki toleransi variasi frekuensi hingga 10% yang mengakibatkan tampilan yang tidak benar-benar layah penuh. Kata kunci: monitor VGA, FPGA

2-D Convolution is a simple mathematical operation which is fundamental to many common image processing operators. Using FPGA to implement the convolver can greatly reduce the DSP's heavy burden in signal processing. But with the limit resource the FPGA can implement a convolver with small 2-D kernel. In this paper, An FIFO type line delayer is presented to serve as the data buffer for convolution to reduce the data fetching operation. A finite state machine is applied to control the reuse of mu...

Due to its potential to greatly accelerate a wide variety of applications, reconfigurable computing has become a subject of a great deal of research. By mapping the compute-intensive sections of an application to reconfigurable hardware, custom computing systems exhibit significant speedups over traditional microprocessors. However, the number and frequency of these hardware-mapped sections of code are limited by the requirement that the speedups provided must outweigh the considerable time cost of configuration. The ability to relocate and defragment configurations on an FPGA can dramatically decrease the overall configuration overhead incurred by the use of the reconfigurable hardware. This increases the viability of mapping portions of the program that were previously considered to be too costly. We therefore explore the adaptation of a simplified Xilinx 6200 series FPGA for relocation and defragmentation. Because of the complexities involved with this structure, we also present a novel architecture designed from the ground up to provide relocation and defragmentation support with a negligible area increase over a generic partially reconfigurable FPGA.

8 au 10 octobre - Premier workshop sur l'utilisation des FPGA dans les centrales nucléaires EDF R&D organise à Chatou, avec l'AIEA en co-sponsor, le "premier atelier sur l'utilisation des FPGA - Field Programmable Gate Array - dans les centrales nucléaires" ("First Workshop on The Applications of Field-Programmable Gate Arrays in Nuclear Power Plants"). Les FPGA, déjà utilisés dans d'autres industries, intéressent de plus en plus le monde du nucléaire, en tant que solution pour la rénovation partielle de systèmes de contrôle-commande mais aussi comme solution alternative aux microprocesseurs. Cet atelier qui se tiendra du 8 au 10 octobre, réunit des exploitants nucléaires (BE, Wolf Creek...), des fournisseurs de systèmes de contrôle-commande (comme AREVA, DS&S, Invensys ou Toshiba), des universitaires, des autorités de sûreté (telles que l'IRSN et la NRC) , ainsi que d'autres industriels concernés par l'usage de cette technologie pour des applications critiques (Airbus, CNES, Lookheed Martin) et des fournisseurs de FPGA (ACTEL).

This paper discusses the design, implementation, experimental validation and performances of a fully digital fast power switch fault detection and compensation for three-phase shunt active power filters. The approach introduced in this paper minimizes the time interval between the fault occurrence and its diagnosis. This paper demonstrates the possibility to detect a faulty switch of the active filter in less than 10 �?s by using simultaneously a "time criterion" and a "voltage criterion". In order to attain this fast detection time a FPGA (Field Programmable Gate Array) is used. The other feature introduced in this approach is that the control scheme used to compensate the current load harmonics and fault tolerant scheme are both programmed in only one FPGA. "FPGA in the loop" prototyping results and fully experimental results based on a real active power filter verify satisfactory performances of the proposed method. © 2008 Elsevier B.V. All rights reserved.

This paper discusses the design, implementation, experimental validation and performances of a fully digital fast power switch fault detection and compensation for three-phase shunt active power filters. The approach introduced in this paper minimizes the time interval between the fault occurrence and its diagnosis. This paper demonstrates the possibility to detect a faulty switch of the active filter in less than 10 �?s by using simultaneously a "time criterion" and a "voltage criterion". In order to attain this fast detection time a FPGA (Field Programmable Gate Array) is used. The other feature introduced in this approach is that the control scheme used to compensate the current load harmonics and fault tolerant scheme are both programmed in only one FPGA. "FPGA in the loop" prototyping results and fully experimental results based on a real active power filter verify satisfactory performances of the proposed method. © 2008 Elsevier B.V. All rights reserved.