This letter¹ presents a method to measure the Young?s moduli of individual thin-film layers in a commercial integrated circuit (IC) foundry process. The method is based on measuring the resonance frequency of an array of micromachined cantilevers and using the presented optimization analysis to determine the elastic modulus of each layer. Arrays of cantilever test structures were fabricated in a commercial CMOS IC process and were released using XeF₂ as a postprocessing etch. A piezoelectric transducer placed under the test chip was used to excite the cantilevers to resonance, and the resonance frequency was measured using a laser Doppler vibrometer. It is reported that excellent agreement for values of Young?s modulus is observed for cantilevers between 200 and 400 mum in length, with average standard deviation being 4.07 GPa.

This paper, which is mostly tutorial in nature, deals with the design of CMOS microelectromechanical systems MEMS using standard microelectronic computer-aided design tools. The proposed case study is an on-chip spectrum analyzer with an electronic mixer and a mechanical filter. Based on both analytical modeling and characterization, the filter is described using an analog hardware description language. System level simulations are then performed using a recently released simulation tool that offer new possibilities regarding the analysis of multidomain, multifrequency designs. Presented results include periodic steady state determination, small-signal analysis and noise investigation. The simulations demonstrate the ability of the proposed system to identify the harmonics of a 50-Hz square-wave signal, owing to the selectivity of the mechanical filter.

The basic principle of operation of each bit in a matrix of image detectors is described, together with the derivation of appropriate operating formulas. The necessary circuitry to make a functional two-dimensional array is also described, including the scanning circuitry integrally constructed with the photodetector matrix. The necessary design considerations for operation of the matrix are discussed in the context of the currently operating 10-by-10 array. Extension of the principles to larger arrays is outlined in the two modes of array scanning considered, with special reference to spatial noise problems. The paper concludes with reference to other applications of the basic principle, such as card reading.

This paper explores the limit of bulk (or partially-depleted SOI) CMOS scaling. A feasible design for 25 nm (channel length) CMOS, without continued scaling of oxide thickness and power supply voltage, is presented. A highly 2D nonuniform profile (super-halo) is shown to yield low off-currents while delivering a significant performance advantage for a 1.0 V power supply. Several key issues, including source-drain doping requirements, band-to-band tunneling, and poly depletion effects, are examined and quantified. It is projected, based on Monte-Carlo simulations, that the delay performance of 25 nm CMOS is 3× higher than 100 nm CMOS, and that the nFET fT exceeds 250 GHz